The present invention relates to nonvolatile semiconductor memory devices, and more particularly to a nonvolatile semiconductor memories having a programming operation.
Flash memories have advanced performances in accessing data, than any other kind of nonvolatile memories such as electrically erasable and programmable read only memories, for a reading and writing (or programming). The merit of high speed operation in the flash memory has been regarded to be very adaptable to portable computing apparatuses, cellular phones or digital still cameras. In general, there are two kinds of the flash memory, such as the NAND-type in which memory cells are connected from a bit line in serial, and the NOR-type in which memory cells are connected to a bit line in parallel. It is well known that the NOR-type flash memory has a competitive speed for data accessing, which makes the NOR-type be more advantageous in a high frequency memory system than the NAND-type.
Typical construction of the cell (or cell transistor) of the flash memory is shown in FIG. 1, which can be used for the multi-bit storage. Source 3 and drain 4, each being formed of N+diffused region in P+semiconductor substrate 2, are separated each other through a channel region which is also defined in substrate 2 . Floating gate 6 is formed over the channel region through thin insulating film 7 which is under 100A, and insulating film 9, such as an Oxe2x80x94Nxe2x80x94O (Oxide-Nitride-Oxide) film, on floating gate 6 isolates control gate 8 from floating gate 6. Source 3, drain 4, control gate 8 and substrate 2 are each connected to their corresponding voltage sources Vs (drain voltage), Vd (source voltage), Vg (gate voltage) and Vb (bulk voltage), for programming, erasing and reading operations.
In programming, as well known, a selected memory cell is programmed by means of a hot electron injection between the channel region and floating gate, in which the source and substrate are held in a ground voltage, a high voltage (e.g., Vg=10V) is applied to the control gate and a voltage to induce the hot electrons therein, 5V through 6V, is provided to the drain. After programmed, a threshold voltage of the selected memory cell is increased therefrom due to deposition of electrons. To read data from the programmed cell, a voltage of about 1V is applied to the drain, a power source voltage (or about 4.5V) is applied to the control gate, and the source is held in the ground voltage. Since the increased threshold voltage of the programmed memory cell acts as an blocking potential even upon the gate voltage during a read-out operation, the programmed cell is considered to as an off-cell which has a threshold voltage between 6V and 7V.
Erasing a memory cell is accomplished by conducting F-N (Fowler-Nordheim) tunneling effect, in which the control gate is coupled to a high negative voltage of about xe2x88x9210V, and the substrate (or bulk) to a positive voltage of about 5V, in order to induce the tunneling therebetween. While this, the drain is conditioned at a high impedance state (or a floating state). A strong electric field induced by the voltage bias conditions, between the control gate and bulk region, causes the electrons to be moved into the source. The F-N tunneling normally occurs when the electric field of 6xcx9c7 MV/cm is developed between the floating gate and bulk region which are separated through the thin insulating film under 100A. The erased cell has a lower threshold voltage than before, and thereby sensed as an on-cell which has a threshold voltage between 1xcx9c3V.
In an usual architecture of a memory cell array in a flash memory, the bulk region (or the substrate) combines active regions of memory cells, so that memory cells formed in the same bulk region are spontaneously erased in the same time. Therefore, units of erasing (hereinafter referred to as xe2x80x9csectorxe2x80x9d, for instance, one sector of 64K) is determined in accordance with the number of separating the bulk regions. Table 1 shows levels of the voltages used in programming, erasing and reading.
In the bias condition shown in FIG. 2A, current about 400 xcexcA flows from the drain terminal, being connected to about 5V, to the source terminal held in 0V. Hot electrons are stacked in floating gate 6, penetrating through tunnel oxide layer 7 interposed between floating gate 6 and the channel region. The large current of 400 xcexcA approximately per cell transistor makes it to be considered that a great number of bits may not be available to be programmed in one time. Usually, almost all of the flash memories employ the programming manner which deal with a unit of byte or word. Programming by a byte (1 byte=8 bits) consumes about 3.2 xcexcA (400 xcexcAxc3x978) per byte, and programming by a word may consume about 6.4 xcexcA (400 xcexcAxc3x9716) per word.
In programming either by a byte or by a word, a number of charge pump circuits are necessary to make the 5V that is bootstrapped from a power supply voltage, increasing the area for lay-out and current consumption. The burden upon programming with increasing circuit area and current dissipation has been issued by an article disclosed in 1996VLSI Circuits by AMD, entitled A 2.7V Only 8Mbx16 NOR Flash Memory in which 1-word is programmed by four bits in four cycle times.
A typical construction of a flash memory device includes, as shown in FIG. 3, memory cell array 10, address buffer 20, row decoder 30, column decoder 40, Y-pass gate circuit 50, data input/output buffers DBF0-DBF15 corresponding to data input/output lines I/O0-I/O15, and write drive circuits W/D0-3 through W/D12-15 which are assigned to bit line selection signals S0-S3. Memory cell array 10 has word lines arranged in a column direction and bit lines, intersecting the word lines, arranged in a row direction. The bit lines are connected to Y-pass gate circuit 50 which selects the bit lines by using decoded signals provided from the column decoder and causes the bit lines to be activated in response to a supply of bit line drive signals into the write drive circuits according to the selection signals.
In a programming operation of the device, input data bits of 16 are first stored in the data buffers DBFi by four bits. In order to program with the unit of four bits, it is necessary to select four bit lines in one time, and the selection signals S0-S3 are applied to their corresponding write drive circuits with the same values. Referring to FIG. 4, the selection signals S0-S3 are enabled in sequence and thereby programming for 1-word is conductive with the unit of four bits throughout four cycle times.
Considering there has been increased of the needs for normal operations conductive even in the basis of a lower power supply voltage as well as an external power supply voltage, programming, erasing and reading must be successfully performed in the condition of a lower Vcc or an wider range (e.g., 2-4V) of voltage. However, since the device aforementioned produces the 5V, to be used in programming with a lower Vcc, by means of charge pump circuits embedded therein, the time for generating the 5V becomes longer. And, even though it is possible to carry out programming in the condition of an wider voltage range by dividing the number of bits that is available to be programmed in one time, it is inevitable to increase the number of cycle times for programming. Furthermore, programming with a high voltage relative to the lower Vcc causes current consumption to be increased more and more every when programming is conductive.
The present invention is intended to solve the problems. And, it is an object of the invention to provide a nonvolatile memory for performing an optimized program operation free from a level of a power supply voltage.
In order to accomplish those objects, a nonvolatile memory device of the invention, operable in a plurality of programming cycles, includes, a memory cell array formed of a plurality of memory cells connected to bit lines and word lines, a plurality of data buffers for receiving a plurality of data bits, a plurality of write drive circuits disposed between the memory cell array and the data buffers, and a circuit for generating a plurality of selection signals for controlling the write drive circuits, in response to a current level of a power supply voltage. The selection signals determines the number of data bits programmed in one of the programming cycles.